drm/i915: Allow pixel clock up to 95% of cdclk on CHV
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Mon, 2 Mar 2015 18:07:16 +0000 (20:07 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 17 Mar 2015 21:30:09 +0000 (22:30 +0100)
commit6cca31950a5df57d89d9cb4f846c96dab902adf9
tree88d15fd74bb21ef3c637d1b16bdcd28670371396
parentde31facda53b595bc42ac87341a9200f1f4eb414
drm/i915: Allow pixel clock up to 95% of cdclk on CHV

Supposedly CHV can sustain a pixel clock of up to 95% of
cdclk, as opposed to the 90% limit that was used old older
platforms. Update the cdclk selection code to allow for this.

This will allow eg. HDMI 4k modes with their 297MHz pixel clock
while still respecting the 320 MHz cdclk limit on CHV.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
Reviewed-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_display.c