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[ARM] Fix mm initialisation with write buffered write allocate caches
authorRussell King <rmk@dyn-67.arm.linux.org.uk>
Wed, 2 Nov 2005 14:11:35 +0000 (14:11 +0000)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Wed, 2 Nov 2005 14:11:35 +0000 (14:11 +0000)
commit6bf7bd6967b1cdde1fe953b0edb951966799fb44
tree4b2537d200a51e13ea9e2b439c58411f7769f325tree | snapshot (tar.gz zip)
parentbfca94590bfd3dcd958c542d2fb6406518150feecommit | diff
[ARM] Fix mm initialisation with write buffered write allocate caches

It seems that without the extra tlb flush, we may end up faulting
during the early kernel initialisation because the TLB can't see
the updated page tables.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/mm/init.c diff | blob | blame | history
Motorola kernel-slsi