ARC: [plat-hsdk] sdio: Temporary fix of sdio ciu frequency
DW sdio controller has external ciu clock divider controlled via
register in SDIO IP. Due to its unexpected default value
(it should divide by 1 but it divides by 8)
SDIO IP uses wrong ciu clock and works unstable
So add temporary fix and change clock frequency from
100000000
to
12500000 Hz until we fix dw sdio driver itself.
Fixes SNPS STAR
9001204800
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>