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clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates
authorMarek Szyprowski <m.szyprowski@samsung.com>
Thu, 26 Jan 2017 12:37:53 +0000 (13:37 +0100)
committerSylwester Nawrocki <s.nawrocki@samsung.com>
Fri, 27 Jan 2017 10:34:00 +0000 (11:34 +0100)
commit698e0d1d22346ef03d7a13fcd9c2cc86a24bf317
tree4effec2a5d8cc0b65e1c9098537a7621491bfbf4tree | snapshot (tar.gz zip)
parent5ccb58968bf7f46dbd128df88f71838a5a9750b8commit | diff
clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates

Default clock configuration applied by the bootloader for TM2 and TM2e
boards includes 250MHz and 278MHz rate for DISP PLL clock. To ensure
such configuration for those boards with 'assigned-clock-*' properties,
parameters for those two additional rates are needed.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
drivers/clk/samsung/clk-exynos5433.c diff | blob | blame | history