clk: samsung: exynos5433: Add clocks for CMU_CAM0 domain
authorChanwoo Choi <cw00.choi@samsung.com>
Tue, 3 Feb 2015 00:13:55 +0000 (09:13 +0900)
committerSylwester Nawrocki <s.nawrocki@samsung.com>
Thu, 5 Feb 2015 18:31:07 +0000 (19:31 +0100)
commit6958f22f39f9292f6e871b4383a11f183c1271ed
tree10cfe77724243ae7bc772c10ed9ae341e717810f
parent8e46c4b84faf317773d5a4ec6d807ceae2d0eb41
clk: samsung: exynos5433: Add clocks for CMU_CAM0 domain

This patch adds the mux/divider/gate clocks for CMU_CAM0 domain which
generates the clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Documentation/devicetree/bindings/clock/exynos5433-clock.txt
drivers/clk/samsung/clk-exynos5433.c
include/dt-bindings/clock/exynos5433.h