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(parent: b728d72) | patch
drm/i915: PSR: Keep sink state consistent with source
authorDurgadoss R <durgadoss.r@intel.com>
Fri, 27 Mar 2015 11:51:32 +0000 (17:21 +0530)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Mon, 30 Mar 2015 14:39:31 +0000 (16:39 +0200)
commit670b90d20a5d71a2f430e0c4b97dac2d17a659b5
treee33e130569f90c21d36891563fa40d68556bca77tree | snapshot (tar.gz zip)
parentb728d7265bfaf125604c48a54d2932add7aebf31commit | diff
drm/i915: PSR: Keep sink state consistent with source

BSpec recommends to keep the main link state consistent
between the source and the sink. As per that, update
the main link state in sink DPCD register to 'active',
for Valleyview based platforms.

Signed-off-by: Durgadoss R <durgadoss.r@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Tested-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_psr.c diff | blob | blame | history