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MIPS: OCTEON: Implement the core-16057 workaround
authorDavid Daney <david.daney@cavium.com>
Thu, 15 Jan 2015 13:11:10 +0000 (16:11 +0300)
committerRalf Baechle <ralf@linux-mips.org>
Fri, 20 Feb 2015 14:30:42 +0000 (15:30 +0100)
commit664d699af24ee73cbc147c4c0f76c8c8ff9ef66f
tree364a6315b49e725a956ef18e08611c87c776b767tree | snapshot (tar.gz zip)
parent69f7cd472493f97976598a8b5b515d9ad4814aa6commit | diff
MIPS: OCTEON: Implement the core-16057 workaround

Disable ICache prefetch for certian Octeon II processors.

Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8938/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h diff | blob | blame | history
Motorola kernel-slsi