arm64: mm: Ensure writes to swapper are ordered wrt subsequent cache maintenance
authorWill Deacon <will.deacon@arm.com>
Fri, 22 Jun 2018 15:23:45 +0000 (16:23 +0100)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Tue, 3 Jul 2018 09:24:52 +0000 (11:24 +0200)
commit64df84dcf1e4dd3b63c60dd6f36473d19060af48
tree3729bc6bf8cf2605c3715f1887394365bd8524f3
parentee6ae5ac75abf889e89c7ad3cdb75bb15d0a6308
arm64: mm: Ensure writes to swapper are ordered wrt subsequent cache maintenance

commit 71c8fc0c96abf8e53e74ed4d891d671e585f9076 upstream.

When rewriting swapper using nG mappings, we must performance cache
maintenance around each page table access in order to avoid coherency
problems with the host's cacheable alias under KVM. To ensure correct
ordering of the maintenance with respect to Device memory accesses made
with the Stage-1 MMU disabled, DMBs need to be added between the
maintenance and the corresponding memory access.

This patch adds a missing DMB between writing a new page table entry and
performing a clean+invalidate on the same line.

Fixes: f992b4dfd58b ("arm64: kpti: Add ->enable callback to remap swapper using nG mappings")
Cc: <stable@vger.kernel.org> # 4.16.x-
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
arch/arm64/mm/proc.S