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(parent: c7d0045) | patch
clk: rockchip: fix the rv1108 clk_mac sel register description
authorElaine Zhang <zhangqing@rock-chips.com>
Mon, 21 Aug 2017 08:16:07 +0000 (16:16 +0800)
committerHeiko Stuebner <heiko@sntech.de>
Tue, 22 Aug 2017 00:55:03 +0000 (02:55 +0200)
commit64a1644bc3baa62b769455d811b7999b9a1c6cd1
tree45c504a9756f007b43db6793b1dd815608749418tree | snapshot (tar.gz zip)
parentc7d0045b08a36c2fb7874efc48d747613c6a1ccfcommit | diff
clk: rockchip: fix the rv1108 clk_mac sel register description

The source clock ordering is wrong, as shown in the TRM:
cru_sel24_con[8]
rmii_extclk_sel
clock source select control register
1'b0: from internal PLL
1'b1: from external IO

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
drivers/clk/rockchip/clk-rv1108.c diff | blob | blame | history