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MIPS: Define some more PIIX4 registers & values
authorPaul Burton <paul.burton@imgtec.com>
Wed, 7 May 2014 11:20:56 +0000 (12:20 +0100)
committerRalf Baechle <ralf@linux-mips.org>
Fri, 30 May 2014 19:01:08 +0000 (21:01 +0200)
commit643c5705bc9d30b64ca320715eb210b853d1f27e
tree714c8f163d64dfe4fc35b37d02a234af6779fa53tree | snapshot (tar.gz zip)
parent76ad023b8925d8b849a9377b77bcfa9a49f57082commit | diff
MIPS: Define some more PIIX4 registers & values

This patch simply adds definitions for some I/O registers in the PIIX4
PM device, and the magic data for a special cycle which must occur on
the PCI bus in order for the PIIX4 to enter a suspend state.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6903/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/include/asm/mips-boards/piix4.h diff | blob | blame | history