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ARC: cacheflush refactor #2: I and D caches lines to have same size
authorVineet Gupta <vgupta@synopsys.com>
Thu, 5 Sep 2013 07:47:49 +0000 (13:17 +0530)
committerVineet Gupta <vgupta@synopsys.com>
Wed, 6 Nov 2013 05:11:37 +0000 (10:41 +0530)
commit63d2dfdbf4b12a6993adf5005fd308d611d453d6
treeb4878a30a70b513ff081f2a4ec0f61a683d0e029tree | snapshot (tar.gz zip)
parentf3e4de327403cee6f76c0dca1b45d6fb0b08daf4commit | diff
ARC: cacheflush refactor #2: I and D caches lines to have same size

Having them be different seems an obscure configuration.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
arch/arc/include/asm/cache.h diff | blob | blame | history
arch/arc/mm/cache_arc700.c diff | blob | blame | history