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ASoC: tlv320aic3x: Mark the RESET register as volatile
authorPeter Ujfalusi <peter.ujfalusi@ti.com>
Fri, 23 Dec 2016 09:21:10 +0000 (11:21 +0200)
committerMark Brown <broonie@kernel.org>
Sat, 31 Dec 2016 18:43:11 +0000 (18:43 +0000)
commit63c3194b82530bd71fd49db84eb7ab656b8d404a
treec21e4e4467dc29598477b248a2aecdb5374174e0tree | snapshot (tar.gz zip)
parenta5de5b74a50113564a1e0850e2da96c37c35e55dcommit | diff
ASoC: tlv320aic3x: Mark the RESET register as volatile

The RESET register only have one self clearing bit and it should not be
cached. If it is cached, when we sync the registers back to the chip we
will initiate a software reset as well, which is not desirable.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Reviewed-by: Jarkko Nikula <jarkko.nikula@bitmer.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/codecs/tlv320aic3x.c diff | blob | blame | history