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platform/x86: intel_pmc_ipc: use gcr mem base for S0ix counter read
authorKuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Sun, 9 Apr 2017 22:00:21 +0000 (15:00 -0700)
committerAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Fri, 28 Apr 2017 18:51:28 +0000 (21:51 +0300)
commit62a7b9c859d09af860c71cfbea4381061975ca72
treebdf4f62e5313716e8653057b6ab1a2d9a16ed212tree | snapshot (tar.gz zip)
parent9d855d468dc655d10be6cb52e36aa0bbfa6f515dcommit | diff
platform/x86: intel_pmc_ipc: use gcr mem base for S0ix counter read

To maintain the uniformity in accessing GCR registers, this patch
modifies the S0ix counter read function to use GCR address base
instead of ipc address base.

Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Tested-by: Shanth Murthy <shanth.murthy@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
arch/x86/include/asm/intel_pmc_ipc.h diff | blob | blame | history
drivers/platform/x86/intel_pmc_ipc.c diff | blob | blame | history