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(parent: 2fad2d9) | patch
x86: cacheinfo: complete L2/L3 Cache and TLB associativity field definitions
authorAndreas Herrmann <andreas.herrmann3@amd.com>
Thu, 9 Apr 2009 13:47:10 +0000 (15:47 +0200)
committerIngo Molnar <mingo@elte.hu>
Fri, 10 Apr 2009 13:41:18 +0000 (15:41 +0200)
commit6265ff19ca08df0d96c859ae5e4dc2d9ad07070e
tree02ce11eaa0d181db68ba992d8e852ba89125b2e7tree | snapshot (tar.gz zip)
parent2fad2d9bb8310889f3261035b594b4e068b6eb8bcommit | diff
x86: cacheinfo: complete L2/L3 Cache and TLB associativity field definitions

See "CPUID Specification" (AMD Publication #: 25481, Rev. 2.28, April 2008)

Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
Cc: Mark Langsdorf <mark.langsdorf@amd.com>
LKML-Reference: <20090409134710.GA8026@alberich.amd.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
arch/x86/kernel/cpu/intel_cacheinfo.c diff | blob | blame | history
kernel source for telekom puls (alcatel/mediatek)