drm/i915: Wait for PHY port ready before link training on VLV/CHV
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Thu, 16 Oct 2014 18:27:34 +0000 (21:27 +0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 4 Nov 2014 22:22:01 +0000 (23:22 +0100)
commit61234fa5e5232c35f87d44d9d596af4b10eac255
treea63664a71dcba97d57a0604dadd381c21493b9a6
parent093e3f134e2eff13503f708b81aecc2501e7aecb
drm/i915: Wait for PHY port ready before link training on VLV/CHV

There's no point in checking if the data lanes came out of reset after
link training. If the data lanes aren't ready link training will fail
anyway.

Suggested-by: Todd Previte <tprevite@gmail.com>
Cc: Todd Previte <tprevite@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Acked-by: Todd Previte <tprevite@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_dp.c