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(parent: 5839783) | patch
bindings: PCI: artpec: correct pci binding example
authorNiklas Cassel <niklas.cassel@axis.com>
Thu, 25 Aug 2016 22:01:56 +0000 (00:01 +0200)
committerRob Herring <robh@kernel.org>
Wed, 31 Aug 2016 15:01:54 +0000 (10:01 -0500)
commit610e12837425e204d1a3bd0182bcdaff1d660e60
tree0fded4c2c057472bb17c2351c802f2c80ace98bftree | snapshot (tar.gz zip)
parent5839783247f416901ea4571882cb81f8354c9d2acommit | diff
bindings: PCI: artpec: correct pci binding example

 - Increase config size. When using a PCIe switch,
   the previous config size only had room for one device.
 - Add bus range. Inherited optional property.
 - Map downstream I/O to PCI address 0. We can map it to any
   address, but let's be consistent with other drivers.

Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt diff | blob | blame | history
Motorola kernel-slsi