clk: rockchip: add special approximation to fix up fractional clk's jitter
authorElaine Zhang <zhangqing@rock-chips.com>
Tue, 1 Aug 2017 16:22:24 +0000 (18:22 +0200)
committerHeiko Stuebner <heiko@sntech.de>
Tue, 8 Aug 2017 15:45:42 +0000 (17:45 +0200)
commit5d890c2df900db0197d46ec75383d7633ef41c82
tree2e9e50736f9d15cddd389b1f968655651d9a15db
parentec52e462564b9c5bfdf1f79638c537c7103e1d2b
clk: rockchip: add special approximation to fix up fractional clk's jitter

>From Rockchips fractional divider description:
  3.1.9  Fractional divider usage
  To get specific frequency, clocks of I2S, SPDIF, UARTcan be generated by
  fractional divider. Generally you must set that denominator is 20 times
  larger than numerator to generate precise clock frequency. So the
  fractional divider applies only to generate low frequency clock like
  I2S, UART.

Therefore add a special approximation function that handles this
special requirement.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
drivers/clk/rockchip/clk.c