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(parent: 4811ff4) | patch
drm/i915: Add chv cmnlane power wells
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Fri, 27 Jun 2014 23:04:08 +0000 (02:04 +0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 8 Aug 2014 15:43:28 +0000 (17:43 +0200)
commit5d6f7ea752228788eddce0b9e268fa1f0eabdd7f
tree2fa7b87dc26a81281bdbc9bf24a190e3f915eb1ftree | snapshot (tar.gz zip)
parent4811ff4f2388727a161ea49c2b0ddca95e44c7f9commit | diff
drm/i915: Add chv cmnlane power wells

CHV has two display PHYs so there are also two cmnlane power wells. Add
the approriate code to power the wells up/down.

Like on VLV we do the cmnreset assert/deassert and the DPLL refclock
enabling at approriate times.

This code actually works on my bsw.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h diff | blob | blame | history
drivers/gpu/drm/i915/intel_pm.c diff | blob | blame | history