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Blackfin: add CPLB entries for Core B on-chip L1 SRAM regions
authorGraf Yang <graf.yang@analog.com>
Fri, 10 Jul 2009 11:34:51 +0000 (11:34 +0000)
committerMike Frysinger <vapier@gentoo.org>
Thu, 16 Jul 2009 05:52:51 +0000 (01:52 -0400)
commit5bc6e3cfe6db5f33c60f042a9ba203431f334756
treeff171234a9d19171e955bc1d05279e38c4b39f97tree | snapshot (tar.gz zip)
parentf574a76a3b19848ac61814756716e26f85f2c3f7commit | diff
Blackfin: add CPLB entries for Core B on-chip L1 SRAM regions

The Blackfin SMP port was missing CPLB entries for Core B on-chip L1 SRAM
regions.  Any code that attempted to use these would wrongly crash due to
a CPLB miss.

Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
arch/blackfin/kernel/cplb-nompu/cplbinit.c diff | blob | blame | history