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(parent: 5d52f48) | patch
iommu/vt-d: Handle Caching Mode implementations of SVM
authorDavid Woodhouse <David.Woodhouse@intel.com>
Sat, 24 Oct 2015 19:06:39 +0000 (21:06 +0200)
committerDavid Woodhouse <David.Woodhouse@intel.com>
Sat, 24 Oct 2015 19:06:39 +0000 (21:06 +0200)
commit5a10ba27d963bc79d6ac2e4996cdbb012195c306
treea7d84b59269fb4b9497533080a5c9f3adda8a2f8tree | snapshot (tar.gz zip)
parent5d52f482ebb7d0845e84cb235700061bc5682adacommit | diff
iommu/vt-d: Handle Caching Mode implementations of SVM

Not entirely clear why, but it seems we need to reserve PASID zero and
flush it when we make a PASID entry present.

Quite we we couldn't use the true PASID value, isn't clear.

Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
drivers/iommu/intel-svm.c diff | blob | blame | history