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(parent: 3880e95) | patch
gpu: host1x: mipi: Registers are 32 bits wide
authorThierry Reding <treding@nvidia.com>
Thu, 2 Oct 2014 12:33:31 +0000 (14:33 +0200)
committerThierry Reding <treding@nvidia.com>
Thu, 13 Nov 2014 15:11:48 +0000 (16:11 +0100)
commit57b17ae71f412b870415b698655f00846e34ce0a
tree8bd069766e5844210032d1c1f1cbd947a5fe6a5dtree | snapshot (tar.gz zip)
parent3880e95f2706e4ad9ba37e382e7f5bb82f911c68commit | diff
gpu: host1x: mipi: Registers are 32 bits wide

On 64-bit platforms an unsigned long would be 64 bit and cause
unnecessary casting when being passed to writel() or returned from
readl(). Make register values 32 bits wide to avoid that.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/gpu/host1x/mipi.c diff | blob | blame | history