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iio: Aspeed ADC
authorRick Altherr <raltherr@google.com>
Tue, 28 Mar 2017 21:52:59 +0000 (14:52 -0700)
committerJonathan Cameron <jic23@kernel.org>
Sat, 1 Apr 2017 10:53:20 +0000 (11:53 +0100)
commit573803234e72d182ec39692770110e574cd5b222
tree9c4dfe0ff91e55844e8d48f5ff605b33149ae793tree | snapshot (tar.gz zip)
parentfb87ecf19e350d73206c5fbf28a28588f171f15dcommit | diff
iio: Aspeed ADC

Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold
interrupts are supported by the hardware but are not currently implemented.

Signed-off-by: Rick Altherr <raltherr@google.com>
Tested-by: Xo Wang <xow@google.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
drivers/iio/adc/Kconfig diff | blob | blame | history
drivers/iio/adc/Makefile diff | blob | blame | history
drivers/iio/adc/aspeed_adc.c [new file with mode: 0644] blob