clk: tegra: pll: Change misc_reg count from 3 to 6
authorBill Huang <bilhuang@nvidia.com>
Thu, 18 Jun 2015 21:28:22 +0000 (17:28 -0400)
committerThierry Reding <treding@nvidia.com>
Fri, 20 Nov 2015 17:04:49 +0000 (18:04 +0100)
commit56fd27b31f1a216623f285bb77b4bcb6129e84c2
tree8bad50beb11b3a32a70a853e23c9203311b333cf
parent204c85d124bd51c0b1c70f1d6b0d853389179d38
clk: tegra: pll: Change misc_reg count from 3 to 6

New SoC's may have more than 3 MISC registers, so bump up the array size
and use a #define to be more informative about the value.

Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk.h