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[COMMON] i2c: exynos5: I2C transfer sequence change for Clock changes
authorKyungwoo Kang <kwoo.kang@samsung.com>
Thu, 4 May 2017 04:50:21 +0000 (13:50 +0900)
committermyung-su.cha <myung-su.cha@samsung.com>
Wed, 9 May 2018 12:14:45 +0000 (21:14 +0900)
commit561f52b36ca85576a156620d2bd23e62c3a878d7
tree297f006f505974e3d2661c10c52ce2286b3fd872tree | snapshot (tar.gz zip)
parent591233eeccd55c74232915f7ce2d8f8fb731381fcommit | diff
[COMMON] i2c: exynos5: I2C transfer sequence change for Clock changes

Transfer sequence has been changed for input clock. We no longer
wait until Master status IDLE between transfer and another transfer.
If we put SFR access or print log for debugging, it will increase
transfer latency.

Change-Id: I512adcbb7394e9566c535020e7aea29d23838188
Signed-off-by: Kyungwoo Kang <kwoo.kang@samsung.com>
drivers/i2c/busses/i2c-exynos5.c diff | blob | blame | history