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MIPS: BMIPS: Flush the readahead cache after DMA.
authorRalf Baechle <ralf@linux-mips.org>
Fri, 27 Mar 2015 14:17:31 +0000 (15:17 +0100)
committerRalf Baechle <ralf@linux-mips.org>
Wed, 1 Apr 2015 15:22:04 +0000 (17:22 +0200)
commit554b7f56b998c72316ab2d5c21963512fd6c9a5e
tree594343e6a7a718994b8c5c73a0d2083d0b0b2945tree | snapshot (tar.gz zip)
parent0acbfc66d09e97e5a01e7a23ac7e99f360ff851bcommit | diff
MIPS: BMIPS: Flush the readahead cache after DMA.

BMIPS 3300/435x/438x CPUs have a readahead cache that is separate from
the L1/L2.  During a DMA operation, accesses adjacent to a DMA buffer
may cause parts of the DMA buffer to be prefetched into the RAC.  To
avoid possible coherency problems, flush the RAC upon DMA completion.

Derived from Kevin Cernekee's https://patchwork.linux-mips.org/patch/9602/.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/include/asm/mach-bmips/dma-coherence.h diff | blob | blame | history