[MIPS] Fix use of smp_processor_id() in preemptible code.
authorPavel Kiryukhin <vksavl@gmail.com>
Tue, 27 Nov 2007 16:20:47 +0000 (19:20 +0300)
committerRalf Baechle <ralf@linux-mips.org>
Sat, 1 Dec 2007 00:39:37 +0000 (00:39 +0000)
commit54fd6441e04696c046d93e4407a9e1ee9b874e51
treeb75c48d3779cb136d09ec7610dc275532b9bfa43
parente1cca7e8d484390169777b423a7fe46c7021fec1
[MIPS] Fix use of smp_processor_id() in preemptible code.

Freeing prom memory: 956kb freed
Freeing firmware memory: 978944k freed
Freeing unused kernel memory: 180k freed
BUG: using smp_processor_id() in preemptible [00000000] code: swapper/1
caller is r4k_dma_cache_wback_inv+0x144/0x2a0
Call Trace:
 [<80117af8>] r4k_dma_cache_wback_inv+0x144/0x2a0
 [<802e4b84>] debug_smp_processor_id+0xd4/0xf0
 [<802e4b7c>] debug_smp_processor_id+0xcc/0xf0
...
CONFIG_DEBUG_PREEMPT is enabled.
--
Bug cause is blast_dcache_range() in preemptible code [in
r4k_dma_cache_wback_inv()].
blast_dcache_range() is constructed via __BUILD_BLAST_CACHE_RANGE that
uses cpu_dcache_line_size(). It uses current_cpu_data that use
smp_processor_id() in turn. In case of CONFIG_DEBUG_PREEMPT
smp_processor_id emits BUG if we are executing with preemption
enabled.

Cpu options of cpu0 are assumed to be the superset of all processors.

Can I make the same assumptions for cache line size  and fix this
issue the following way:

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
include/asm-mips/cpu-features.h