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MIPS: MSI: Update MSI handling for XLP
authorJayachandran C <jchandra@broadcom.com>
Wed, 7 Jan 2015 11:28:28 +0000 (16:58 +0530)
committerRalf Baechle <ralf@linux-mips.org>
Wed, 1 Apr 2015 15:21:49 +0000 (17:21 +0200)
commit53f676977dddaa6784dab7b058cfe8895e3c8772
tree8f49568829fe71a39db9f0ee81555d22644ec3datree | snapshot (tar.gz zip)
parenta3613be442aaf435d7d3b224c81cea0b0f702d6acommit | diff
MIPS: MSI: Update MSI handling for XLP

The per-cpu interrupt ACK using EIRR has to be done just once after
all the bits in the status register are processed.

PIC ack has to be done once in case of MSI, and for every interrupt
in case of MSI-X

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8887/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/pci/msi-xlp.c diff | blob | blame | history