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drm/tegra: sor: Write correct head state registers
authorThierry Reding <treding@nvidia.com>
Thu, 30 Jul 2015 16:47:07 +0000 (18:47 +0200)
committerThierry Reding <treding@nvidia.com>
Thu, 13 Aug 2015 11:47:56 +0000 (13:47 +0200)
commit51511d05defe92715c19c3e583c9d1ac1c82e1e6
treeed99b1b09875c65286362cf4f55672a9cc6a22ddtree | snapshot (tar.gz zip)
parent8044449556338fb27b1a03f6b1dbbdbc59e4ebfacommit | diff
drm/tegra: sor: Write correct head state registers

The head state registers are per head, so they must be properly indexed.
This has worked fine so far because all boards with eDP use it as the
primary output, so it is very likely to end up attached to head 0.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/gpu/drm/tegra/sor.c diff | blob | blame | history