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(parent: fc755c8) | patch
clk: st: STiH407: Support for clockgenC0
authorGabriel FERNANDEZ <gabriel.fernandez@st.com>
Tue, 15 Jul 2014 15:20:27 +0000 (17:20 +0200)
committerMike Turquette <mturquette@linaro.org>
Tue, 29 Jul 2014 05:36:54 +0000 (22:36 -0700)
commit51306d56ba81dc2bded042188706481f0c84d379
treed6f61bcde203dc15a849cd948096bf5cd15c303ctree | snapshot (tar.gz zip)
parentfc755c8bc8f155980077cb015020ec0a97ebc5c6commit | diff
clk: st: STiH407: Support for clockgenC0

The patch added support for DT registration of ClockGenC0
It includes 2 c32 type PLL and a 660 Quadfs.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
drivers/clk/st/clkgen-fsyn.c diff | blob | blame | history
drivers/clk/st/clkgen-pll.c diff | blob | blame | history