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(parent: b278268) | patch
powerpc/885: set SDCR to 0x40
authorChristophe Leroy <christophe.leroy@c-s.fr>
Thu, 4 Feb 2016 10:07:48 +0000 (11:07 +0100)
committerScott Wood <oss@buserror.net>
Wed, 9 Mar 2016 16:44:16 +0000 (10:44 -0600)
commit501ea76687ef16a88a96cc9848e5d760f1c68e4e
treef4fa260e3230d7325c679cd9661556aaec5f41a4tree | snapshot (tar.gz zip)
parentb278268b63258c86e1df155c461df1259c9c6f05commit | diff
powerpc/885: set SDCR to 0x40

The MPC885 reference manual says that SDCR shall have value 0x40, but
most exemples set SDCR to 0x1
With 0x1 in SDCR, we observe TX underruns on SCC when using it in
QMC mode.
According the NXP technical support, this is a copy/paste error from
MPC860 reference manual, 0x40 being the only value supported
by the MPC885 HW.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
arch/powerpc/sysdev/cpm1.c diff | blob | blame | history