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mmc: renesas_sdhi_core: on R-Car 2+, make use of CBSY bit
authorWolfram Sang <wsa+renesas@sang-engineering.com>
Wed, 28 Jun 2017 15:21:56 +0000 (17:21 +0200)
committerUlf Hansson <ulf.hansson@linaro.org>
Wed, 30 Aug 2017 12:01:26 +0000 (14:01 +0200)
commit4dc48a95fa20832c972c667efa5518bcf3ece6be
treef9ca2fa07862f353af505159e46d3148fbc4bcbdtree | snapshot (tar.gz zip)
parent01ffb1ae84dc1df6fc0c077aad0de597c6ddc05bcommit | diff
mmc: renesas_sdhi_core: on R-Car 2+, make use of CBSY bit

Most registers need to wait until the command is completed, not
necessarily until the bus is free. At least, R-Car 2+ SoCs can signal
that via the CBSY bit, so let's use it there instead of SCLKDIVEN to
save a little bit of delay.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
drivers/mmc/host/renesas_sdhi_core.c diff | blob | blame | history