drm/i915: fix up adjusted_mode tracking for interlaced modes
authorDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 3 May 2013 09:49:51 +0000 (11:49 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Mon, 6 May 2013 09:23:46 +0000 (11:23 +0200)
commit4d8a62eac3caad710ef030aab25248d56693a8f1
tree05e92d2ea67564ca0696ab7448337ddcc96cb77d
parent0e50e96bf2d89c3415cb68aead301f485938f1ca
drm/i915: fix up adjusted_mode tracking for interlaced modes

With the hw state readout&check code it's important that the values we
keep around are the canonical ones. Unfortunately when adding the pipe
timings readout support I've missed that the write side adjusts the
timings in the pipe config.

Fix this up and so prevent the unsightly WARN noise in dmesg. This
regression has been introduced in

commit 1bd1bd806037af04dd1d7bdd39b2b04090c10d2c
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Mon Apr 29 21:56:12 2013 +0200

    drm/i915: hw state readout support for pipe timings

Reported-by: Paulo Zanoni <przanoni@gmail.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_display.c