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author	Damien Lespiau <damien.lespiau@intel.com>
	Fri, 6 Mar 2015 18:50:48 +0000 (18:50 +0000)
committer	Daniel Vetter <daniel.vetter@ffwll.ch>
	Tue, 17 Mar 2015 21:30:06 +0000 (22:30 +0100)
commit	4c6c03be125e9d8477c2d8ef3c3280270956b1fe
tree	3880d0ccd3efafcc7b64e5be9760dc022675bdd1	tree \| snapshot (tar.gz zip)
parent	5575f03a603d267e84ab3727f7241b8be5f7d8ee	commit \| diff

drm/i915/skl: Make gen8_irq_power_well_post_enable() take a pipe mask

While we only need to restore pipe B/C interrupt registers on BDW when
enabling the power well, skylake a bit more flexible and we'll also need
to restore the pipe A registers as it has its own power well that can be
toggled.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

drivers/gpu/drm/i915/i915_irq.c		diff \| blob \| blame \| history
drivers/gpu/drm/i915/intel_drv.h		diff \| blob \| blame \| history
drivers/gpu/drm/i915/intel_runtime_pm.c		diff \| blob \| blame \| history

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