clk: samsung: exynos5433: Add missing clocks for CMU_FSYS domain
authorChanwoo Choi <cw00.choi@samsung.com>
Mon, 2 Feb 2015 14:24:05 +0000 (23:24 +0900)
committerSylwester Nawrocki <s.nawrocki@samsung.com>
Wed, 4 Feb 2015 17:58:14 +0000 (18:58 +0100)
commit4b8013554b0454984e71bc20bc31966886079e15
treeaec461bd118b077e7326389b1b625035454ffdce
parent5785d6e61f27f7af4d239c1647d5a22e0dbff19b
clk: samsung: exynos5433: Add missing clocks for CMU_FSYS domain

This patch adds the mux/divider/gate clocks for CMU_FSYS domain which
contains the clocks of USB/UFS/SDMMC/TSI/PDMA IPs.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
drivers/clk/samsung/clk-exynos5433.c
include/dt-bindings/clock/exynos5433.h