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ASoC: wm8940: Fix setting PLL Output clock division ratio
authorAxel Lin <axel.lin@gmail.com>
Mon, 24 Oct 2011 03:32:41 +0000 (11:32 +0800)
committerMark Brown <broonie@opensource.wolfsonmicro.com>
Mon, 24 Oct 2011 12:09:42 +0000 (14:09 +0200)
commit49fa4d9b5aeafb985abe8cb8cdf6432690c49ad3
tree4c3aee893aa2818d83a1ff5f9691b5749b9cb1b9tree | snapshot (tar.gz zip)
parent753ddf52153b60be924109df3bebab0cd60b3297commit | diff
ASoC: wm8940: Fix setting PLL Output clock division ratio

According to the datasheet:
The PLL Output clock division ratio is controlled by BIT[5:4] of
WM8940_GPIO register(08h).
Current code read/write the WM8940_ADDCNTRL(07h) register which is wrong.

Signed-off-by: Axel Lin <axel.lin@gmail.com>
Acked-by: Liam Girdwood <lrg@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
sound/soc/codecs/wm8940.c diff | blob | blame | history
Motorola kernel-slsi