x86, Calgary: Increase max PHB number
authorDarrick J. Wong <djwong@us.ibm.com>
Thu, 24 Jun 2010 21:26:47 +0000 (14:26 -0700)
committerIngo Molnar <mingo@elte.hu>
Fri, 25 Jun 2010 14:14:58 +0000 (16:14 +0200)
commit499a00e92dd9a75395081f595e681629eb1eebad
tree763ab3fff9baa4f7b09ae97379321df5ccfa2724
parent890ffedc7c3e95595926379e28ad2e16e7d7c613
x86, Calgary: Increase max PHB number

Newer systems (x3950M2) can have 48 PHBs per chassis and 8
chassis, so bump the limits up and provide an explanation
of the requirements for each class.

Signed-off-by: Darrick J. Wong <djwong@us.ibm.com>
Acked-by: Muli Ben-Yehuda <muli@il.ibm.com>
Cc: Corinna Schultz <cschultz@linux.vnet.ibm.com>
Cc: <stable@kernel.org>
LKML-Reference: <20100624212647.GI15515@tux1.beaverton.ibm.com>
[ v2: Fixed build bug, added back PHBS_PER_CALGARY == 4 ]
Signed-off-by: Ingo Molnar <mingo@elte.hu>
arch/x86/kernel/pci-calgary_64.c