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MIPS: sc-mips: L2 cache is inclusive of L1 dcache for CM3
authorPaul Burton <paul.burton@imgtec.com>
Fri, 19 Aug 2016 17:13:36 +0000 (18:13 +0100)
committerRalf Baechle <ralf@linux-mips.org>
Tue, 3 Jan 2017 15:48:40 +0000 (16:48 +0100)
commit48ed33c1b3737eb1324c1ae023a8eeccad60cef9
tree2f0bba73f2155877df0790bbc863036f89bfb9e2tree | snapshot (tar.gz zip)
parentd66f99bc46925831236cf2335fcc6087d34e2195commit | diff
MIPS: sc-mips: L2 cache is inclusive of L1 dcache for CM3

In systems with CM3 & higher, the L2 cache is inclusive of the L1
dcache. Indicate this such that cpu_has_inclusive_pcaches evaluates true
and we avoid some unnecessary cache ops during DMA cache maintenance.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14018/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/mm/sc-mips.c diff | blob | blame | history