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ARM: KVM: add missing dsb before invalidating Stage-2 TLBs
authorMarc Zyngier <marc.zyngier@arm.com>
Fri, 21 Jun 2013 12:08:47 +0000 (13:08 +0100)
committerChristoffer Dall <christoffer.dall@linaro.org>
Wed, 26 Jun 2013 17:50:04 +0000 (10:50 -0700)
commit479c5ae2f8a55509b691494cd13691d3dc31d102
tree6892951511aa62357eec0266f1dc6ca1d4bc9652tree | snapshot (tar.gz zip)
parent6a077e4ab9cbfbf279fb955bae05b03781c97013commit | diff
ARM: KVM: add missing dsb before invalidating Stage-2 TLBs

When performing a Stage-2 TLB invalidation, it is necessary to
make sure the write to the page tables is observable by all CPUs.

For this purpose, add a dsb instruction to __kvm_tlb_flush_vmid_ipa
before doing the TLB invalidation itself.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
arch/arm/kvm/interrupts.S diff | blob | blame | history