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(parent: 80ca69f) | patch
MIPS: mm: c-r4k: Flush scache to avoid cache aliases
authorLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Tue, 21 Jan 2014 09:48:48 +0000 (09:48 +0000)
committerRalf Baechle <ralf@linux-mips.org>
Wed, 26 Mar 2014 22:09:19 +0000 (23:09 +0100)
commit4676f9359fa5190ee6f42bbf2c27d28beb14d26a
treed509258e6c14b290235e816eecc0e9237163bf7dtree | snapshot (tar.gz zip)
parent80ca69f40f26fb016e6d863b48fe1a1abdae8840commit | diff
MIPS: mm: c-r4k: Flush scache to avoid cache aliases

There is a chance for the secondary cache to have memory
aliases. This can happen if the bootloader is in a non-EVA mode
(or even in EVA mode but with different mapping from the kernel)
and the kernel switching to EVA afterwards. It's best to flush
the icache to avoid having the secondary CPUs fetching stale
data from it.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
arch/mips/mm/c-r4k.c diff | blob | blame | history
Motorola kernel-slsi