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ARM: 7164/3: PL330: Fix the size of the dst_cache_ctrl field
authorJavi Merino <javi.merino@arm.com>
Wed, 16 Nov 2011 11:36:39 +0000 (12:36 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Wed, 15 Feb 2012 21:10:49 +0000 (21:10 +0000)
commit4272f98a1ae81709fc5c804c33c044064e419cd9
tree0e3af4e730a6f1bbec98f3e4808dd272e8ae8e58tree | snapshot (tar.gz zip)
parent8e43a905dd574f54c5715d978318290ceafbe275commit | diff
ARM: 7164/3: PL330: Fix the size of the dst_cache_ctrl field

dst_cache_ctrl affects bits 3, 1 and 0 of AWCACHE but it is a 3-bit
field in the Channel Control Register (see Table 3-21 of the DMA-330
Technical Reference Manual) and should be programmed as such.

Reference: <1320244259-10496-3-git-send-email-javi.merino@arm.com>

Signed-off-by: Javi Merino <javi.merino@arm.com>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/include/asm/hardware/pl330.h diff | blob | blame | history
Motorola kernel-slsi