drm/i915/cnl: Fix PLL mapping.
authorRodrigo Vivi <rodrigo.vivi@intel.com>
Tue, 3 Oct 2017 22:08:58 +0000 (15:08 -0700)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Tue, 17 Oct 2017 00:11:02 +0000 (17:11 -0700)
commit41e64c1ac73bbc2380d7b85357a4b693043a5ba8
treee06c09c8f3ea1283e93b11708e99fac5f0f8753d
parentfbe776cc3a753618877f7ce87a28ae3480743348
drm/i915/cnl: Fix PLL mapping.

On PLL Enable sequence we need to "Configure DPCLKA_CFGCR0 to turn on
the clock for the DDI and map the DPLL to the DDI"

So we first do the map and then we unset DDI_CLK_OFF to turn the clock
on. We do this in 2 separated steps.

However, on this second step where we should only unset the off bit we are
also unmapping the ddi from the pll. So we end up using the pll 0
for almost everything. Consequently breaking cases with more than one
display.

Fixes: 555e38d27317 ("drm/i915/cnl: DDI - PLL mapping")
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Kahola, Mika <mika.kahola@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: James Ausmus <james.ausmus@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171003220859.21352-2-rodrigo.vivi@intel.com
(cherry picked from commit 87145d95c3d8297fb74762bd92e022d7f5cc250c)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
drivers/gpu/drm/i915/intel_ddi.c