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MIPS: asm: r4kcache: Build flushing code for instruction cache
authorLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Mon, 16 Dec 2013 11:24:13 +0000 (11:24 +0000)
committerRalf Baechle <ralf@linux-mips.org>
Wed, 26 Mar 2014 22:09:18 +0000 (23:09 +0100)
commit41e62b0411d84e3d92deac79b83b0bacca4b9a52
tree563a98f0d83d77c4b3d414651646ef55c1cc9815tree | snapshot (tar.gz zip)
parentca750649e08ce37bd3873e1026dc245811adf7a8commit | diff
MIPS: asm: r4kcache: Build flushing code for instruction cache

Build code to invalidate an address range in the  instruction cache
using the Hit Invalidate cache operation.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
arch/mips/include/asm/r4kcache.h diff | blob | blame | history
Motorola kernel-slsi