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(parent: b453de0) | patch
x86, amd: Extend AMD northbridge caching code to support "Link Control" devices
authorHans Rosenfeld <hans.rosenfeld@amd.com>
Mon, 24 Jan 2011 15:05:42 +0000 (16:05 +0100)
committerIngo Molnar <mingo@elte.hu>
Wed, 26 Jan 2011 07:28:23 +0000 (08:28 +0100)
commit41b2610c3443e6c4760e61fc10eef73f96f9f6a5
treec88ed29b417ef4e034c177428cdec320b8a66659tree | snapshot (tar.gz zip)
parentb453de02b786c63b8928ec822401468131db0a9bcommit | diff
x86, amd: Extend AMD northbridge caching code to support "Link Control" devices

"Link Control" devices (NB function 4) will be used by L3 cache
partitioning on family 0x15.

Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com>
Cc: <andreas.herrmann3@amd.com>
LKML-Reference: <1295881543-572552-4-git-send-email-hans.rosenfeld@amd.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
arch/x86/include/asm/amd_nb.h diff | blob | blame | history
arch/x86/kernel/amd_nb.c diff | blob | blame | history
include/linux/pci_ids.h diff | blob | blame | history