UPSTREAM: arm64: Add workaround for Cavium erratum 27456
authorAndrew Pinski <apinski@cavium.com>
Thu, 25 Feb 2016 01:44:57 +0000 (17:44 -0800)
committerSami Tolvanen <samitolvanen@google.com>
Thu, 29 Sep 2016 17:52:56 +0000 (10:52 -0700)
commit3e64a8612dfa8738b95ad904a454b859ec9d9174
tree611b1f34ae50f7d0efcbe88b7e40f9838dbc8664
parentd5f46e4b247971c9c10f902151dcf7df8c750b1c
UPSTREAM: arm64: Add workaround for Cavium erratum 27456

On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
instructions may cause the icache to become corrupted if it contains
data for a non-current ASID.

This patch implements the workaround (which invalidates the local
icache when switching the mm) by using code patching.

Signed-off-by: Andrew Pinski <apinski@cavium.com>
Signed-off-by: David Daney <david.daney@cavium.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Change-Id: I60e6d17926b067a4e022d7b159e239114303a547
(cherry picked from commit 104a0c02e8b1936c049e18a6d4e4ab040fb61213)
Signed-off-by: Sami Tolvanen <samitolvanen@google.com>
Documentation/arm64/silicon-errata.txt
arch/arm64/Kconfig
arch/arm64/include/asm/cpufeature.h
arch/arm64/kernel/cpu_errata.c
arch/arm64/mm/proc.S