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(parent: 1a0abcd) | patch
clk: rockchip: fix the incorrect pclk_edp div width for RK3399
authorXing Zheng <zhengxing@rock-chips.com>
Wed, 18 Jan 2017 04:20:56 +0000 (12:20 +0800)
committerHeiko Stuebner <heiko@sntech.de>
Wed, 18 Jan 2017 10:23:36 +0000 (11:23 +0100)
commit3e1531dbc333997ae19324993119c42436d3e6b6
tree31dc140969b600f03204227fa909efb63daadee9tree | snapshot (tar.gz zip)
parent1a0abcd634dc3caf0d15cb8625e3f43d77b37031commit | diff
clk: rockchip: fix the incorrect pclk_edp div width for RK3399

The range of the  pclk_edp_div_con is [13:8] and 6 bits, not 5.

Reported-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Tested-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
drivers/clk/rockchip/clk-rk3399.c diff | blob | blame | history