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(parent: 3eb6156) | patch
clk: tegra: Fix pllx dyn step calculation
authorRhyland Klein <rklein@nvidia.com>
Thu, 14 Jan 2016 19:24:35 +0000 (14:24 -0500)
committerThierry Reding <treding@nvidia.com>
Tue, 2 Feb 2016 14:49:24 +0000 (15:49 +0100)
commit3dad5c5fa1d24c3bbb3e9e8ac0c52f35e045b807
treed3b7c9b1ec316b1bc5838f754c43f8b8a3250049tree | snapshot (tar.gz zip)
parent3eb61566a6efc5a56ebe1e6b86519bc5e0b39003commit | diff
clk: tegra: Fix pllx dyn step calculation

The logic for calculating the input rate used when figuring out the
proper dynamic steps for pllx was incorrect. It is supposed to be
calculated using parent_rate / m but it was just using the parent rate
directly, therefore using the wrong step values.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-tegra210.c diff | blob | blame | history