drm/i915: Configure GEN6_RP_DOWN_TIMEOUT on CHV
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Mon, 19 Jan 2015 11:50:49 +0000 (13:50 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 27 Jan 2015 08:50:45 +0000 (09:50 +0100)
commit3cbdb48fbe7f975d96cfd7dddc3bfb17c9a01583
tree5574c195d0c6f8b8253cc099f9c944c826b68950
parentcad725fe37454ac42fa909d589271ce6f065682c
drm/i915: Configure GEN6_RP_DOWN_TIMEOUT on CHV

CherryViewA0_iGfx_BIOS_DRIVER_PUNIT_spec_y14w28d5 tells us not to enable
the RP down timeout interrupt, and says that the timeout value is hence
not used. We do enable that interrupt currently though, so leaving the
timeout as 0 results in very poor performance as the GPU frequency keeps
dropping constantly. So just program the register with the recommended
value.

Leaving the interrupt enabled doesn't seem to do any harm so far. So
I've decided to leave it on for now, just to avoid making CHV a
special case.

This fixes the performance regression from:
 commit 5a0afd4b78ec23f27f5d486ac3d102c2e8d66bd7
 Author: Deepak S <deepak.s@linux.intel.com>
 Date:   Sat Dec 13 11:43:27 2014 +0530

    drm/i915/chv: Use timeout mode for RC6 on chv

Cc: Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Deepak S<deepak.s@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_pm.c