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(parent: e5e6f68) | patch
arm: zynq: Label whole PL part as fpga_full region
authorMichal Simek <michal.simek@xilinx.com>
Tue, 14 Feb 2017 16:40:21 +0000 (17:40 +0100)
committerMichal Simek <michal.simek@xilinx.com>
Mon, 21 Aug 2017 11:52:49 +0000 (13:52 +0200)
commit3c220bf420908319cc1dc0715eb822e6a7c663e3
tree8f0fc6f0f66d891592960dd6b50b6a538446360ftree | snapshot (tar.gz zip)
parente5e6f6872c7a6e2b15295574ecab8391c03808cdcommit | diff
arm: zynq: Label whole PL part as fpga_full region

This will simplify dt overlay structure for the whole PL.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arch/arm/boot/dts/zynq-7000.dtsi diff | blob | blame | history