clk: rockchip: Add pclk_peri to critical clocks on RK3066/RK3188
authorRomain Perier <romain.perier@gmail.com>
Sun, 23 Aug 2015 09:32:37 +0000 (11:32 +0200)
committerStephen Boyd <sboyd@codeaurora.org>
Thu, 10 Sep 2015 20:55:30 +0000 (13:55 -0700)
commit3bba75a2ec32bd5fa7024a4de3b8cf9ee113a76a
tree33c33a65294d3e3ee6907fffc2e8fdab3fa070eb
parent1166160ab531198f7abc773992c0e04d0f9b7600
clk: rockchip: Add pclk_peri to critical clocks on RK3066/RK3188

Now that the rockchip clock subsystem does clock gating with GPIO banks,
these are no longer enabled once during probe and no longer stay enabled
for eternity. When all these clocks are disabled, the parent clock pclk_peri
might be disabled too, as no other child claims it. So, we need to add pclk_peri
to the critical clocks.

Signed-off-by: Romain Perier <romain.perier@gmail.com>
Tested-by: Michael Niewoehner <linux@mniewoehner.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/rockchip/clk-rk3188.c