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(parent: 9a28977) | patch
drm/i915: PIPE_CONTROL TLB invalidate requires CS stall
authorJesse Barnes <jbarnes@virtuousgeek.org>
Thu, 25 Oct 2012 19:15:47 +0000 (12:15 -0700)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Sun, 11 Nov 2012 22:51:37 +0000 (23:51 +0100)
commit3ac7831314eba873d60b58718123c503f6961337
tree62e2042a11d641e20ff782f1cce19623c165d96ftree | snapshot (tar.gz zip)
parent9a28977181724ebbd9bdc45291cf29da55a729eecommit | diff
drm/i915: PIPE_CONTROL TLB invalidate requires CS stall

"If ENABLED, PIPE_CONTROL command will flush the in flight data  written
out by render engine to Global Observation point on flush done. Also
Requires stall bit ([20] of DW1) set."

So set the stall bit to ensure proper invalidation.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Antti Koskipää <antti.koskipaa@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_ringbuffer.c diff | blob | blame | history
Motorola kernel-slsi